WLCSP FIFO Technology Forum
Date: 2018/6/20 (Wednesday)
Time: 08:30 –16:30
Venue: 3F, Sheraton Hotel Hsinchu, 新竹喜來登大飯店
No. 265, Dong Sec. 1, Guangming 6th Rd, Zubei City 302, Hsinchu County, Taiwan
新竹縣竹北市光明六路東一段256號
Registration Price: NTD$4,500
Forum Name: WLCSP FIFO (Fan-in/ Fan-out) Technology Forum
研討會主題：晶圓級扇入扇出型封裝技術研討會
Forum Outline
High performance temporary wafer bonding technology are vital essential for 2.5D and 3D IC technologies. Many new materials and process selections have been coming together with equipment suppliers. However, the equipment cost of ownership is still very high and the process performance in terms of throughput and wafer broken are concerned. The forum is intended to deliver industry market the best in class wafer bonding solution for various temporary bond process applications in carried wafers and bonding materials.
Die cracking and chipping have become very critical in wafer thinning for tiny and high stacked die attached assembly especially for SSD high die stacked packaging. Stealth dicing technology that uses a laser to cut a wafer into a die form to obtain chipping or cracking free processing. The low K wafer from nanometer process technology node in wafer processing requires chipping free dicing technology to ensure a stringent device integrity without causing defects. Stealth dicing is an essential technology to meet the harsh conditions for high end semiconductor application of 2.5D/3D assembly. Thus the stealth dicing is emerging to address die chipping or cracking effectively.
Chip attach (Die attach) after dicing or wire bonding has become the bottleneck for semiconductor assembly processing for its critical aspects in die stacking not only on quality but throughput as well There are various technologies available for chip attach processing such as conventional mass-reflow chip attach with high temperature curing through furnace which is concerning tensile stress between low k die and substrate, Thermal Compression Bonding (TCB), is concerning its low throughput with high equipment investment, and recently a new chip bonding technology is emerging- Lase Assistant Bonding (LAB) which is to provide low temperature bonding die by die with good bonding uniformity. LAB is an innovative technology for Fine Pitch Flip Chip or 2.5D/3D stacking die assembly on high ball counts of signal I/O and achieving low form factor packages, High-End Package with large sized die and substrate.
Learn how New Generation Projection Litho SCANNER overcomes legacy stepper patterning limitation: No-Stitch Full-Field Imaging, – No undesired Stitch Area Artifacts – No In-Shot (Intra-Field) Residual Mag Error – No Edge Protection and Edge Exposure – and all with the Lowest Projection Litho CoO available. And, also find out why the DSC300 Gen3 Projection Scanner is the best tool for today’s industry trends toward larger die & packages for high performance computing applications, complex high-density FO-WLP designs, as well as, trends toward higher integration and aggregated modules to support future IoT and 5G Network applications. The unique advantages of the Full-Field Scanning Technology is also available for large panels for SAP and FO-PLP processes.
Copper pillar bump maintains its competitive position on fine pitches to make it an excellent interconnect choice for embedded/application processors, power management, baseband, ASICs and SOCs for mobile applications. Not only for SOC applications, memory especially for DDRX DRAM which needs high speed application for PC in order to match to CPU applications. More and more semiconductor applications require fine pitch copper pillar bump to inter-connect its signal I/O that will be driving for huge demand on CuP bumped wafers beyond 2020. The low cost of ownership CuP plating process technology is essential to allow for smaller devices, reduce the number of substrate package layers and thus to enhance RoHS/green compliance, low cost and electro-migration performance.
For the fine pitch bumping defects due to process deviation, foreign materials, deformation of bump, bump coplanarity have become major yield killers in bumping processing. Thus, an effective AOI tool with consistent repeatability of defect sensing, resolution and throughput is vital critical for yield enhancement. Not only for bumping application, AOI is essentially applied for defect inspection post die sawing especially for high die stack assembly applications. However, there are various options for process applications with different lighting sources, 2D/3D capability, Realtime Defect Analysis are to be studied to be best fitted for process effectiveness and efficiency. The AOI solution provides useful methodology for catching missing bumps and other bump defect and dicing defects, bump height, diameter and coplanarity, reducing potential problems in flip chip die attach.
高效能臨時晶圓鍵合技術對於2.5D和3D IC封裝至關重要。許多新材料和製程的搭配已經與設備供應商一起出現。但是，設備建置成本仍然居高不下，並與單位產出和晶圓破片息息相關。本論壇旨在為業界提供最佳晶圓鍵合解決方案，探討承載晶圓，鍵合材料中的各種臨時鍵合技術及應用。
對於微小化和高堆疊晶片片封裝，特別是對於SSD多層晶片堆疊封裝，晶片薄化和切割已成為非常關鍵的問題。隱形切割技術使用雷射將晶圓切割達到無晶崩裂痕工序。切割Low K晶圓以確保元件完整性而不會造成缺陷。隱形切割是滿足2.5D / 3D封裝高端半導體應用的關鍵技術。因此，隱形切割的出現，得以有效解決切割崩裂的問題。
切割完後晶片貼合已經成為半導體組裝產出的瓶頸，晶片堆疊的關鍵在於品質及產出，傳統的Mass Reflow 晶片熱壓合（TCB）技術，其低產量和高設備投資的限制，最近出現了一種新的晶片鍵合技術 - Laser Assistant Bonding (LAB），它可以通過裝置提供低溫粘合技術，具有良好的粘合均勻性。 LAB是一種創新技術，用於高信號I / O數和實現低封裝尺寸的高精度FCCSP或2.5D / 3D堆以及具有大尺寸晶片和基板的高端封裝。
新一代投影微影技術掃瞄儀如何克服傳統的步進圖案限制：無縫全視野成像 - 沒有多餘的針跡區域偽影 - 無插入式（場內）殘留磁塊錯誤 - 無邊緣保護和邊緣曝光 - 全部皆以最佳的投影微影技術成本達到。此外，DSC300 Gen3投影掃描儀是現今產業趨勢的最佳利器，適用於大型裸晶和封裝之高性能計算應用、複雜的高密度FO-WLP設計以及朝著更高集成度和聚合模組的趨勢以支持未來的物聯網和5G網絡應用。全域掃描技術的獨特優勢也適用於SAP和FO-PLP工藝的大型面板。
銅柱凸塊持續其在精細線距上的競爭優勢，使其成為嵌入式/應用處理器，電源管理，基頻，ASIC和移動應用SOC的良好鍵結之首選。不僅適用於SOC應用，特別適用於需要高速PC應用的DDRX DRAM的內存，以便與CPU應用相匹配。越來越多的半導體應用需要精細的銅柱凸點來互連其信號輸入輸出，這將推動2020年以後的CuP凸塊晶片的巨大需求。低成本CuP電鍍技術允許設計更小的器件，減少襯底封裝層的數量，從而提高RoHS /綠色合規性，低成本和消除電子遷移等特性。
由於製程偏差導致細間距凸起缺陷，異物，凸塊變形，凸塊共面性等，已成為凸塊製程中的主要品質殺手。因此，具有優質的缺陷檢測，分辨率和有效的AOI工具對提高產量至關重要。 AOI主要應用於晶片切割後的缺陷檢測，特別適用於高堆疊組裝應用。但是，對於具有不同光源的應用方面，2D / 3D功能以及及時缺陷分析，以尋求製程最佳化。 AOI解決方案提供了有用的方法來捕獲缺失的凸塊和其他凸塊缺陷以及切割缺陷，凸塊高度，直徑和共面性等，從而減少FCCSP晶片貼合中的潛在問題。
